发明名称 |
Clock enable system |
摘要 |
A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.
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申请公布号 |
US2003224745(A1) |
申请公布日期 |
2003.12.04 |
申请号 |
US20020159177 |
申请日期 |
2002.05.30 |
申请人 |
GEALOW JEFFREY C.;BARBER THOMAS J.;BIRK PALLE;SOERENSEN JOERN |
发明人 |
GEALOW JEFFREY C.;BARBER THOMAS J.;BIRK PALLE;SOERENSEN JOERN |
分类号 |
G06F1/32;H04B1/18;H04B1/38;(IPC1-7):H04B1/18 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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