| 摘要 |
The invention relates to an integrated semiconductor circuit (1) provided with capacitors (10, 20), each of which having a first electrode (11, 21), a second electrode (12, 22) with a doped layer (13, 23), and a dielectric (14, 24). The poly-depletion effect of the doped layers used leads to a distortion of the capacitance characteristic curve whereby traditionally requiring each capacitor (10, 20) to have a supplementary circuit for correcting the characteristic curve. The prior art already provides a parallel connection of two capacitors (10, 20), which have a largely linear capacitance-voltage characteristic curve and, therefore, are used without the provision of linearizing supplementary circuits. According to the invention, the areas (A1, A2) of doped layers (13, 23) of both capacitors (10, 20) have different dimensions, whereby an even greater linearization of the capacitance-voltage characteristic curve is attained without the connection of any additional capacitors. |
