发明名称 |
Synchronizing and aligning differing clock domains |
摘要 |
Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.
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申请公布号 |
US2003226052(A1) |
申请公布日期 |
2003.12.04 |
申请号 |
US20020160621 |
申请日期 |
2002.05.31 |
申请人 |
HILL KEVIN M.;MATTHEWS CHRIS D.;BASHIR AMIR A.;ARENDT KEVIN E.;VOLK ANDREW M. |
发明人 |
HILL KEVIN M.;MATTHEWS CHRIS D.;BASHIR AMIR A.;ARENDT KEVIN E.;VOLK ANDREW M. |
分类号 |
G06F1/12;(IPC1-7):G06F1/12 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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