发明名称 |
Interleaver for iterative decoder |
摘要 |
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.
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申请公布号 |
US2003225985(A1) |
申请公布日期 |
2003.12.04 |
申请号 |
US20030384430 |
申请日期 |
2003.03.08 |
申请人 |
WILLIAM J. RUENLE VP & CFO |
发明人 |
SUZUKI HIROSHI;KRAFFT STEPHEN EDWARD |
分类号 |
H03M13/25;H03M13/27;H03M13/29;H03M13/41;H04L1/00;(IPC1-7):G06F12/00 |
主分类号 |
H03M13/25 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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