摘要 |
The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines (BL) basing upon a change, after the pre-charge, of the potential at each bit line (BL), without changing the column address. Even if a write bit error occurs, no write error is issued so long as the number of bits can be relieved by an ECC circuit. |
申请人 |
KABUSHIKI KAISHA TOSHIBA, KAWASAKI |
发明人 |
TANAKA, TOMOHARU;MOMODOMI, MASAKI;KATO, HIDEO;NAKAI, HIROTO;TANAKA, YOSHIYUKI;SHIROTA, RIICHIRO;ARITOME, SEIICHI;ITOH, YASUO;IWATA, YOSHIHISA;NAKAMURA, HIROSHI;ODAIRA, HIDEKO;OKAMOTO, YUTAKA;ASANO, MASAMICHI;TOKUSHIGE, KAORU |