| 摘要 |
<p>A computer system comprising a plurality of data processing elements connected through a shared communication bus to a memory so that for a given computer cycle at least one of the elements assumes control of the bus for accessing address in memory. The computer system having memory access circuitry connected between the data processing elements and memory which has first and second buffer units for storing prefetched bursts of data from the memory. The buffer circuit also having control logic for prefetching data in sequential bursts from the memory and storing the prefetched burst in the first or second buffer units and the control logic monitors the buffer units and the address to be accessed in memory to determine in which buffer the next fetched burst should be stored.</p> |
