发明名称 Priority based simultaneous multi-threading
摘要 A simultaneous multi-threaded architecture combines OS priority information with thread execution heuristics to provide dynamic priorities for selecting thread instructions for processing. The dynamic priority of a thread is determined by adjusting a heuristic measure of the thread's execution dynamics with a priority-dependent scaling function determined from the OS priority of the thread. An SMT processor includes logic for calculating a scaling function for each thread scheduled on the processor, tracking the threads' heuristics, and combing the scaling function and heuristic information into a dynamic priority for each thread. Instructions are selected for execution from among the scheduled threads according to the threads' dynamic priorities.
申请公布号 US6658447(B2) 申请公布日期 2003.12.02
申请号 US19970889795 申请日期 1997.07.08
申请人 INTEL CORPORATION 发明人 COTA-ROBLES ERIK
分类号 G06F9/38;G06F9/48;(IPC1-7):G06F9/00 主分类号 G06F9/38
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