Semiconductor device with low power consumption memory circuit

摘要

The present invention relates to a system LSI consolidating a logic circuit and an SRAM circuit. More specifically, the present invention relates to a semiconductor device which can reduce a leakage current and the power consumption in the standby state.The logic circuit in the system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing a leakage current. At the same time, the SRAM circuit controls a substrate bias to reduce the leakage current.