Data transfer on reconfigurable chip

摘要

A reconfigurable chip having reconfigurable elements uses an interconnection system which reduces the maximum signal rise and fall time. In one embodiment, the maximum rise and fall time is reduced by providing bypass paths. In another embodiment, buffers are used to reduce signal rise and fall times. Connections between each of the elements are provided by either providing a loop path or by providing bidirectional arrangements of the buffers.