| 摘要 |
A serial differential link glitcher system and method which allow for verification of error recovery by an interfaced or linked architecture system. The system and method provide accurate, reliable, and more assured fault simulation, such as noisy interface and dirty link simulations, within an interfaced or linked architecture system for verification of such error recovery and verifies and checks data at a lower level between interfaced devices. The system and method verify disparity errors between interfaced devices and also perform verification of error recovery between electrically linked devices or optically linked devices. At least two devices are coupled together by communication lines. Normal mode allows for normal operation of and normal communication between the at least two devices, and glitch mode provides fault simulation and disparity errors and phase inversion between the at least two devices for testing error recovery of the system. Proper polarity of the communication lines is maintained between the at least two devices when the system is in normal operation mode. The polarity of the communication lines between the at least two devices is switched and inverted when the system is in glitch mode wherein phase inversion and disparity errors in the communication lines are created. The glitcher switch system comprises a switch and a control circuit. The switch allows switching between the communication mode, that is, between the normal operation mode and the glitch mode. The control circuit controls the switch in placing the system in the normal operation mode or the glitch mode.
|
