| 摘要 |
A frame timing lock detector circuits and a methods of frame timing lock detection for a digital communications system. A known data sequence is extracted from a received radio signal and multiplied, in a multiplier, together with a reference signal that includes the symbols of the known data sequence raised to the power of a multiple of three. The phase of the multiplier output is measured and an average of an absolute value of this measured phase is compared with a threshold to detect correct frame timing lock.
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