| 摘要 |
The present invention provides a mechanism whereby caching operations, such as prefetch and copyback operations, can be initiated by an external direct memory access (DMA) controller. This allows the DMA controller to govern the inclusion as well as exclusion of data from a processor cache in such as way as to avoid unnecessary cache faults, and to thereby improve system performance. Thus, the present invention effectively provides a synchronization mechanism between an external DMA controller and a processor cache.
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