发明名称 Method and system for keeping two independent busses coherent following a direct memory access
摘要 Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.
申请公布号 US6658520(B1) 申请公布日期 2003.12.02
申请号 US20000671516 申请日期 2000.09.26
申请人 INTEL CORPORATION 发明人 BENNETT JOSEPH A.
分类号 G06F13/28;(IPC1-7):G06F1/00 主分类号 G06F13/28
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