| 摘要 |
An improved clock generation circuit that utilizes a multi-phase PLL architecture is provided as well as a method for generating multiple phase outputs. The clock generation circuit can produce multiple phase outputs with the oscillator only producing approximately one-half of those multiple phase outputs. The other half of the phase outputs come from a set of delay circuits external to the oscillator. In this fashion, the oscillator can operate at relatively high frequencies yet not suffer the consequences of trying to decrease the tap-to-tap delay using additional series delay elements if numerous phase outputs are needed. Instead, one-half of the taps are provided external to the oscillator. Thus, the phase outputs from the oscillator are interleaved with phase outputs from an external set of delay circuits, where the oscillator is under frequency lock control using a first PLL and the external delay circuits maintain the frequency lock of the oscillator, yet are delayed in phase by virtue of a phase lock control of a second PLL. The combination of dual PLLs ensures consistent phase alignment between the oscillator phase outputs and the external delay circuit phase outputs. Phase control is ensured through the second PLL and, importantly, regularly spaced phase outputs produced in an interleaved fashion can be achieved for high density phase outputs exceeding, for example, 8, 16, or even 32 multiple phase outputs from the PLL circuit.
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