发明名称 LAYOUT VERIFICATION METHOD AND PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To sharply shorten a time for DRC (Design Rule Check) verification when already verified layout pattern data are partially changed. SOLUTION: The mismatching part of layout pattern data before a change and layout pattern data after the change is extracted as a changed region in a step S12. Then, the outer shape of the changed region is enlarged only by predetermined dimensions toward the outside in a step S13 so that an area to be verified can be set. Then, the DRC of the region to be verified is executed in a step S14, and a DRC result 7 is outputted in a step S15. When any error is generated, an error associated only with the layout pattern within the changed region and an error associated with both the layout pattern in the changed region and the layout pattern outside the changed region are classified as a true error. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003337843(A) 申请公布日期 2003.11.28
申请号 JP20020144818 申请日期 2002.05.20
申请人 NEC MICRO SYSTEMS LTD 发明人 WAKITA SHINICHI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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