| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a fast processor having high performance in processing which is not affected by the influence of latency. <P>SOLUTION: A sum-up device is constituted with a pipeline-type adder 202, a shift register 204 and a shit-step number control section 206. The output of the pipeline-type adder 202 is connected with the shift register 204, and the output of the shift register 204 is connected with an input of the pipeline-type adder 202. The number of the shift steps of the shift register 204 is controlled by the shift-step number control section 206. <P>COPYRIGHT: (C)2004,JPO |
