发明名称 Structure and method for parallel testing of dies on a semiconductor wafer
摘要 In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.
申请公布号 US2003219913(A1) 申请公布日期 2003.11.27
申请号 US20030340558 申请日期 2003.01.09
申请人 AZALEA MICROELECTRONICS CORPORATION 发明人 POURKERAMATI ALI;PARK EUNGJOON
分类号 G01R31/28;(IPC1-7):H01L21/00 主分类号 G01R31/28
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