发明名称 |
Parity prediction for arithmetic increment function |
摘要 |
The present invention provides a method and apparatus to check the arithmetic increment function through prediction of the change in the bit-level parity of the result by means of a series of identical cells connected in a linear array. The array predicts the change in parity produced by the arithmetic increment function which allows the increment function to be checked in an efficient manner. The advantages of the present invention are that the parity check design saves hardware cost over prior schemes that require duplication of incrementers and comparison of the results and schemes that require generation of parity after incrementing, and that the iterative, identical cell implementation of the parity predictor is well-suited for current VLSI and future digital logic circuits as they progress towards molecular, self-assembling components.
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申请公布号 |
US2003220955(A1) |
申请公布日期 |
2003.11.27 |
申请号 |
US20020151038 |
申请日期 |
2002.05.21 |
申请人 |
SHACKLEFORD J. BARRY;TANAKA MOTOO |
发明人 |
SHACKLEFORD J. BARRY;TANAKA MOTOO |
分类号 |
G06F11/00;(IPC1-7):G06F11/00 |
主分类号 |
G06F11/00 |
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