| 摘要 |
A method and system for characterizing and validating the timing of LVS circuits. In particular, based upon an input of a topological description of an LVS circuit (e.g., a netlist) and other circuit parameters such as a clock specification or any mutex or logical correlations between inputs and ignored devices, an output of all paths and arcs from primary inputs to sense amplifier inputs is generated. A complete set of valid input vectors required to exercise all paths is generated. These vectors may then be exhaustively simulated to provide input waveforms to all sense amplifiers. |
