| 摘要 |
There is disclosed a semiconductor memory device including a memory cell array containing a plurality of banks each having one or more blocks, a data erase circuit configured to erase data from selected blocks in banks at a unit of block, and an automatic multi-block erase circuit configured to enable a data read circuit configured to read data from memory cells provided in one bank, when data erase operation for all erase-object blocks in the one bank is completed, while continuing a data erasing operation of a next erase-object block included in another bank. |
