| 摘要 |
An integrated memory has a respective terminal for a clock signal and a data clock signal and also a data terminal. For a write operation, the memory accepts a write command on account of the clock signal and, in a manner time-delayed with respect thereto, a plurality of data at the data terminal on account of the data clock signal. An access controller serves for controlling an access to a memory cell array of the memory for the parallel writing of the accepted data to selected memory cells. The access to the memory cell array is triggered by the access controller by a phase-shifted clock signal before the clock signal has a next rising edge after the acceptance of the data. It is thus possible to increase the effective writing time from the application of the write command to the closing of a memory bank by a precharge command.
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