| 摘要 |
<p>According to the invention, one element (EC) in one of several orthogonal OVSF codes with at most 2BM elements is generated dynamically. A logic circuit (2, 3) provides an intermediary word (NC') having: low-order B bits which are identical to the low-order B bits in the reverse order in a word that is representative of the code number (NC) designating the code from among SF = 2B possible codes with SF elements, and having high-order BM-B bits at a predetermined state. An ET circuit (4) multiplies the bits in the intermediary word (NC') and a word that is representative of a determined position (PC) of the element in the code, such as to produce a product word (PC') with BM bits. A circuit (5) applies an EXCLUSIVE-OR operation to the bits of the product word in order to generate the code element (EC). In this way, no code is stored.</p> |
