| 摘要 |
This invention relates to fault-tolerant computer systems. Bus interface uni ts (BIUs) perform fault detection, identification, and reconfiguration for all information transfers between redundant central processing units (CPUs) and memory or input/output (I/O) i n a mesh interconnected array of a computer system. Errors are detected by self- checking within the BIUs, signal parity checks by the BIUs, cross channel comparisons, and mesh transaction assessments. If self implicating errors are detected, the corresponding BIU is shut down, BIU configuration vectors are asserted onto the mesh and a consensus configurati on vector is generated. If synchronization or memory bus errors are detected, correspondi ng error messages are asserted on the mesh and a reconfiguration algorithm is perform ed in order to generate a consensus configuration vector. Fault identification and mesh reconfiguration for the mesh is performed such that no faulty unit remains active in decision making after reconfiguration, and the number of good units isolated during reconfiguratio n is minimized.
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