| 摘要 |
The present invention provides a method and apparatus for determining the strongest and weakest paths from a supply of a gate comprised in an integrated circuit to an output node of the gate and from ground to the output node of the gate. The apparatus comprises a computer capable of being configured to execute a rules checker program. When the rules checker program is executed by the computer, it analyzes information relating to the network and determines the strongest and weakest paths from the supply to the output node of the gate and from ground to the output node of the gate. The rules checker program calculates the effective widths of the PFET and NFET networks in the gate being evaluated and uses this information to determine the strongest and weakest paths from the supply to the output node of the gate and from ground to the output node of the gate. Once the strongest and weakest paths have been determined, information relating to the strongest and weakest paths is utilized by the rules checker to model the gate as an inverter having a single PFET and a single NFET. Two models are generated for this purpose. One model corresponds to the strongest PFET and the weakest NFET and a second model corresponds to the strongest NFET and the weakest PFET. The PFET-to-NFET ratios of the models can be used to determine various design characteristics of the gate, such as, for example, the noise immunity of the gate.
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