发明名称 |
Variable length coding packing architecture |
摘要 |
Embodiments of a variable length coding packing architecture are discussed. In this regard, an example method of packing selected portions of separate bit strings into a buffer is presented. The example method comprises using multiplexers (MUXes) to select the desired portions of the separate bit strings to be packed in the buffer, and using MUXes to order the bits of the selected portions for packing in particular buffer locations.
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申请公布号 |
US6653953(B2) |
申请公布日期 |
2003.11.25 |
申请号 |
US20010935524 |
申请日期 |
2001.08.22 |
申请人 |
INTEL CORPORATION |
发明人 |
BECKER RICARDO A.;ACHARYA TINKU |
分类号 |
H04N7/26;H03M7/30;H03M7/40;(IPC1-7):H03M7/00 |
主分类号 |
H04N7/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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