Flash memory array architecture and method of programming, erasing and reading thereof

摘要

A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bitlines. Each of the pair of transistors in each set is associated with a different one of an adjacent pair of word lines. The array is configured by providing elongated source/drain regions of zigzag configuration in side-by-side relation. Each bit line connects to a pair of adjacent source/drain regions in alternating manner along the bitline length.