| 摘要 |
Circuit blocks each of which is within a predetermined scale are formed based on a read-out net list. Each circuit block is subjected to a dynamic timing analysis, and a delay characteristic library including obtained analysis results is generated. A static timing analysis is performed based on the delay characteristic library. In this manner, the transmission delay of a desired signal path is analyzed in such a manner that the circuit to be analyzed that is indicated by the net list is regarded to be constructed by the above circuit blocks. A delay characteristic analyzing method is provided that can shorten the processing time while maintaining a high degree of freedom of LSI designing and high accuracy of critical path determination in transistor-level full custom LSI designing.
|
