| 摘要 |
A floating point inverse square root circuit is disclosed. The circuit is configured to receive a floating point value comprised of a sign bit, an exponent field, and a mantissa field. The inverse square root circuit includes a lookup table configured to receive at least a portion of the floating point value and further configured to generate an initial approximation (x0) of the inverse square root of the floating point value from the received portion of the floating point value. The inverse square root circuit further includes a first estimation circuit that receives the initial approximation from the lookup table and at least a portion of a value L derived from the floating point value mantissa field (M) and further configured to produce a first approximation (x1) of the floating point value's inverse square root based upon L and x0 where x1 is a more accurate estimate of the inverse square root than x0. The first estimation circuit may include first, second, and third fixed point multiplication units and first and second fixed point adders where the first multiplication unit is configured to square the initial approximation x0, the first fixed point adder is configured to receive as its inputs the initial approximation x0 and the output of a first shift register that receives the initial approximation x0 as its input, and the second multiplication unit is configured to multiply the output of the first multiplication unit by the initial approximation x0. The third multiplication unit may be configured to multiply the output of the second multiplication unit by L and the second adder may be configured to add the output of the first adder with a shifted and 2's complemented version of the output of the third multiplier to produce the first approximation x1. The value L may comprise the normalized mantissa field if the exponent of the floating point value is odd and two times the normalized mantissa field if the exponent of the floating point value is even.
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