| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor technique whereby the manufacturing time of a semiconductor device having memory and logic circuits mounted thereon in a mixed way is shortened. <P>SOLUTION: Contact plugs 17, 67 are formed in an interlayer insulating film 14 and stopper films 13, 15 while exposing the top surfaces of the contact plugs 17, 67 from the stopper film 15 to the outside. Then, an interlayer insulating film 18 is formed on the stopper film 15 and the plugs 17, 67 to form in the interlayer insulating film 18 openings 69 for exposing the contact plug 67 to the outside. Without etching the stopper film 15, only the interlayer insulating film 18 is so etched as to be able to form the openings 69, and a time required to form the openings 69 can be shortened. <P>COPYRIGHT: (C)2004,JPO |
