| 摘要 |
PROBLEM TO BE SOLVED: To provide a pipe line processing circuit where reduction in throughput caused by an unnecessary standby operation of a flip flop is avoided. SOLUTION: When a busy signal is inputted from a following stage at a timing of delivering data to the following stage, FFs 311, 321, and 331 for holding data continuously hold the data without delivery to the following stage in a following clock period. When the busy signal is inputted from a following stage with a timing of receiving the data from a precedent data, the data is usually received from the precedent data without stopping the receiving operation of the data in the following clock period. The reduction of throughput caused by the unnecessary standby operation of the FF can be avoided, and operation speed can be increased. COPYRIGHT: (C)2004,JPO
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