发明名称 |
INTEGRATED CIRCUIT CHIP INCLUDING TEST ELEMENT GROUP CIRCUIT AND FABRICATION METHOD THEREOF |
摘要 |
<p>PURPOSE: An integrated circuit chip including a test element group circuit and a fabrication method thereof are provided, which performs an EDS(Electric Die Sorting) test and a TEG(Test Element Group) test at the same time in each integrated circuit chip formed on a wafer without increasing test time. CONSTITUTION: The semiconductor integrated circuit device formed on a semiconductor wafer(1) includes at least one first pad(22), and a plurality of second pads connected to corresponding internal circuits respectively, and the first test element group circuit(23) connected to the first pad. The above internal circuits and the first test element group circuit are tested at the same time. The first pad is a non-bonding pad, and the second pads are bonding pads.</p> |
申请公布号 |
KR20030089021(A) |
申请公布日期 |
2003.11.21 |
申请号 |
KR20020026906 |
申请日期 |
2002.05.15 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHO, UK RAE;KIM, SU CHEOL;SON, GWON IL |
分类号 |
G01R31/28;G11C29/00;H01L21/66;H01L21/822;H01L23/544;H01L23/58;H01L27/04;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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