| 摘要 |
The circuits for detecting start and stop, respectively, detect the conditions for start and stop on a data signal (SDA) associated with a clock signal (SCL) according to teh IIC protocol. The circuit for detecting start comprises a counter (30) for counting the pulses of a reference clock signal (CLK) when an initialization (reset) signal (RST) is produced by a first detector (20) of a falling front (trailing edge) of the data signal (SDA) and producing a validation signal (COUNT) when the number of counted pulses reaches a predefined number (NB); and a second detector (40) for storing in memory the validation signal (COUNT) when a falling front of the clock signal (SCL) is detected. The circuit (claimed) for detecting start comprises the first detector (20) containing a bistable whose data input is connected to the ground, whose clock input receives the data signal (SDA), and whose output delivers the initialization signal (RST). The second detector (40) contains a bistable whose data input receives the validation signal (COUNT), whose clock input receives the clock signal (SCL), and whose output delivers the start signal (START). The circuit comprises a supplementary initialization circuit for producing a second initialization signal equal to the inverse of the clock signal (SCL) and synchronized on the reference clock signal (CLK), where the second signal is used to initialize the first and/or the second detector (20,40). The circuit (claimed) for detecting stop comprises a detector for producing a stop signal (STOP) when a rising front (leading edge) of the data signal (SDA) is detected after the detection of a rising front of the clock signal (SCL). The detector comprises a bistable whose data input receives a supply voltage, whose clock input receives the data signal (SDA), and whose output delivers the stop signal (STOP). The circuit (claimed) for detecting the data transmitted according to the IIC protocol comprises the circuit for detecting start and the circuit for detecting stop. |
