| 摘要 |
<P>PROBLEM TO BE SOLVED: To lower increase of parasitic capacitance due to the formation of an electrode connection with a bit line in regard to a semiconductor memory device and a method of manufacturing the same. <P>SOLUTION: Overhang sections 3 which are led out in the shape of an overhang are provided in the areas deviated in a direction along a gate wiring from an active region 4, particularly at the area deviated by half-pitch to a contact electrode 2 for an upper layer from the active layer 4 within a memory array region including an accumulated capacitance in which at least a part thereof is located at the layer 1 higher than the bit line 1. <P>COPYRIGHT: (C)2004,JPO |
