| 摘要 |
PROBLEM TO BE SOLVED: To provide a processing system capable of transmitting data at a further high speed through a bus between a peripheral device and a processor without reducing the clock frequency of the according to the peripheral device having a low-speed storage device, and an access control circuit and method therefor to the storage device. SOLUTION: In a bus signal detection part 201, the access to the storage device 20b is detected from a bus address signal transmitted to an address bus ADR, and the memory address of the storage device 20b transmitted to a data bus DAT is latched by a bus signal retention part 202 and an address signal retention part 203. The access to the memory device 20b is performed by use of the latched memory address, and the writing processing and reading processing to the storage device 20b are executed. COPYRIGHT: (C)2004,JPO
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