发明名称 |
Quadrature receiver sampling architecture |
摘要 |
Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.
|
申请公布号 |
US2003215027(A1) |
申请公布日期 |
2003.11.20 |
申请号 |
US20020184766 |
申请日期 |
2002.06.28 |
申请人 |
BROADCOM CORPORATION ,A CALIFORNIA CORPORATION |
发明人 |
YU TOMMY;JAFFE STEVEN;KRAFFT STEPHEN EDWARD |
分类号 |
H03K9/00;H04L27/00;(IPC1-7):H03K9/00 |
主分类号 |
H03K9/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|