| 摘要 |
A memory element in an integrated circuit including several levels of conductive materials separated by insulating levels, each of which is capable of being crossed by conductive vias of an intercalary via level, and at least two connection rails, including several assemblies of successive interconnected areas and vias, a first assembly being formed of a zigzag running from a first metal level to a last metal level and back to the first metal level between a first end and a second end, each of the other assemblies being connected to one of the connection rails, the first end of the zigzag being connected to an initial assembly among the other assemblies.
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