发明名称 |
Halbleiter-IC-Vorrichtung und deren Herstellungsverfahren |
摘要 |
A plurality of cells (5) providing constituent elements for a semiconductor integrated circuit are provided in and on a major surface of a semiconductor substrate (31) of a semiconductor integrated circuit chip (20). A plurality of wires are each provided between a cell (5) and a cell (5) to provide cell-to-cell wires (8). A plurality of dummy wires (4) are connected to an internal power source terminal (7) of a second power source potential (VSS) which is different from a first power source terminal (VDD). A capacitance (C) is created between the dummy wire (4) and the semiconductor substrate to prevent a voltage fluctuation at the power source. The dummy wires (4) are selectively cut off the internal power source terminal of the second potential (VSS) to correct a wrong connection line or a signal delay time. |
申请公布号 |
DE69034109(D1) |
申请公布日期 |
2003.11.20 |
申请号 |
DE1990634109 |
申请日期 |
1990.07.20 |
申请人 |
KABUSHIKI KAISHA TOSHIBA, KAWASAKI |
发明人 |
WADA, SATOSHI;WAKABAYASHI, SHINICHI;FUKUDA, MASAYO |
分类号 |
H01L21/82;H01L23/522;H01L23/528;H01L27/118;(IPC1-7):H01L27/10;H01L21/60;H01L23/50 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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