DUTY-CYCLE-EFFICIENT SRAM CELL TEST

摘要

A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains the multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.