The invention relates to an electronic component (10) comprising an integrated circuit that is provided with a core with functional flip-flops. A part of the function flip-flops are linked as input FFs (18) with input pins (19) of the component (10) and a part of the functional flip-flops are linked as output FFs (23) with output pins (27) of the component (10). The aim of the invention is to fulfil high timing requirements while not complicating the verification of timing and logic. For this purpose, the input FFs (18) and the output FFs (23) are arranged in such a manner that they form at least one input block (11) and one output block (13) each with respective clock domains that differ from the clock domains of the remaining core (12).
