| 摘要 |
PURPOSE: A clock distribution circuit of a semiconductor memory device is provided to reduce the operation timing between the data buffers placed at the wide area of the semiconductor memory device. CONSTITUTION: A clock distribution circuit of a semiconductor memory device includes a clock driving device(11), a clock transmission line(12), a plurality of clock synthesizing devices(15,16) and a plurality of data buffers(17,18). In the clock distribution circuit, the clock driving device(11) drives the inner clock signal synchronized with the external clock signal inputted from outside and the clock transmission line(12), formed in the form of folded clock distribution line, transmits the inner clock signal driven by the clock driving device(11). And, the plurality of clock synthesizing devices(15,16) synthesize the clock signals at the nodes corresponding to the clock transmission line(12).
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