| 摘要 |
<p>A phase processor (230) is disclosed which is configured to receive processed radar return data from a left radar channel (224), a right radar channel (228), and an ambiguous radar channel (226). The phase processor (230) comprises a plurality of phase detectors (510, 512, 514) each with an input and a reference input. The phase detectors (510, 512, 514) are configured to determine a phase difference between radar return data received at the input and radar return data received at the reference input.</p> |
