发明名称 DMA circuit with bit handling function
摘要 A DMA circuit include a read address register for storing a read address; a write address register for storing a write address; an OR register for storing data; a logic operation selection register for storing information indicating whether to write the read data without change or to carry out the OR operation; and a data calculation circuit for carrying out control either of writing the read data from the read address to the write address without change, or of writing the resultant data of the OR operation between the read data and the data stored in the OR register to the write address, in response to the information stored in the logic operation selection register. The DMA circuit can improve the controllability of the entire system.
申请公布号 US2003217203(A1) 申请公布日期 2003.11.20
申请号 US20020291653 申请日期 2002.11.12
申请人 MIYAKE TAKASHI 发明人 MIYAKE TAKASHI
分类号 G06F13/28;G06F13/38;(IPC1-7):G06F13/28 主分类号 G06F13/28
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