发明名称 |
Programmable delay circuit within a content addressable memory |
摘要 |
An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.
|
申请公布号 |
US6650575(B1) |
申请公布日期 |
2003.11.18 |
申请号 |
US20010040714 |
申请日期 |
2001.12.28 |
申请人 |
NETLOGIC MICROSYSTEMS, INC. |
发明人 |
KHANNA SANDEEP |
分类号 |
G11C7/10;G11C15/00;H03K5/00;H03K5/15;(IPC1-7):G11C7/00;G11C21/00;G11C7/02;G11C8/00;H03D13/00 |
主分类号 |
G11C7/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|