| 摘要 |
A semiconductor memory device has a memory cell array which includes memory cells arranged in a matrix form on a semiconductor substrate, each of the memory cells including a MISFET which has a source, a drain, a channel body and a gate electrode, each of the memory cells having a first state and a second state; word lines, each of which is connected to the gate electrodes of the memory cells arranged in a first direction; first bit lines, each of which is connected to the drains of the memory cells arranged in a second direction, the bit lines being formed in a first wiring layer located above the semiconductor substrate; and a second bit line which is formed in a second wiring layer located above the first wiring layer, the second bit line being connected to the first bit lines via bit line switches.
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