发明名称 |
Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array |
摘要 |
A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input. A logic gate array comprises a plurality of vertical ultrathin transistors coupled together.
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申请公布号 |
US6649476(B2) |
申请公布日期 |
2003.11.18 |
申请号 |
US20010788109 |
申请日期 |
2001.02.15 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
FORBES LEONARD |
分类号 |
H01L21/822;H01L21/82;H01L21/8234;H01L27/04;H01L27/088;H01L27/118;H03K19/096;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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