发明名称 |
Semiconductor memory device with reduced its chip area and power consumption |
摘要 |
One (first level shift circuit) of first and second level shift circuits is provided in a local word-drive-line driving circuit located near memory cell arrays. The second level shift circuit is provided in a global word-drive-line driving circuit located remote from the memory cell arrays.
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申请公布号 |
US6650590(B2) |
申请公布日期 |
2003.11.18 |
申请号 |
US20020103141 |
申请日期 |
2002.03.22 |
申请人 |
KABUSHIKI KAISHA TOSHIBA;FUJITSU LIMITED |
发明人 |
INABA TSUNEO;KOHNO FUMIHIRO;TSUCHIDA KENJI;IKEDA TOSHIMI |
分类号 |
G11C11/407;G11C8/08;G11C8/14;G11C11/401;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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