| 摘要 |
The invention relates to a method of performing a multiprecision modular multiplication phase with two operands (A, B), the multiplication phase comprising at least two sub-phases, namely a partial multiplication phase and a partial reduction phase. The inventive method is characterised in that the two sub-phases are interleaved and make use of the same multiplier circuit (150). The cryptoprocessor comprises a multiplication function (120), a storage module (140), a multiplication module (150) with registers (A, Q, R0, R1, RU0, RU1, Rt0, Rt1, Rk0, Rk1) and a multiplier circuit and is characterised in that it also comprises multiplexers (MUX0, MUX1, MUX2) which link the registers to the multiplier circuit. |
