| 摘要 |
A rate generator circuit for generating test signals whose timings vary in a pulse by pulse basis for testing semiconductor devices includes: a reference clock to determine a basic operational timing of the semiconductor test system; a pattern generator which stores rate data indicating timings of each pulse for the test signals for reading out a plurality of the rate data in parallel in synchronism with a system clock; a temporary storage for temporary storing and transferring the plurality of rate data; a timing generator for generating a plurality of sets of a timing pulse and timing data, each of the rate data being a combination of a coarse timing and a fine timing, at least one set of the timing pulse and the timing data is produced based on a sum of all of the plurality of the rate data and a fine timing of a previous cycle of the system clock, and each of the other sets of the timing pulse and the timing data is produced based on corresponding one of the plurality of the rate data and the fine timing of the previous cycle; and a waveform generator for adding a delay time indicated by the timing data to corresponding one of the timing pulse and converting the plurality of the timing pulses provided with the delay times into a series signal. |
