| 摘要 |
PROBLEM TO BE SOLVED: To provide a digital signal transmitter and receiver in which a transmitter side can control selection or revision of hardware circuits of the receiver. SOLUTION: A video signal and an audio signal subject to compression encoding by encoders 001, 011 are buffered tentatively with hardware configuration information by FIFO memories 002, 012, 021, packet processing circuits 003, 013, 0022 apply packet processing and the result is stored in memories 004, 014, 023. On the other hand, a PMT(program map table) generating circuit 031 sets PMT describing PID(packet ID) or the like of the video signal, the audio signal and the hardware configuration information into a packet, a packet multiplex controller 030 reads the data stored in the memories 004, 014, 023 as a time multiplex signal in the unit of packets in matching with video/audio encoding speeds, applies time multiplexing to the data with other sets of time multiplex signals and the result is outputted from a terminal 056 as a bit stream signal. |
