| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a CPU synchronous detection processor and a method therefor in which synchronous signals distributed at intervals of 512 bits contained in received serial data are speedily detected. <P>SOLUTION: In the CPU synchronous detection processor, the serial data having synchronous bits distributed at the intervals of 512 bits are received at intervals of 8 bits, the serial data received at the intervals of 8 bits are written in continuous addresses at intervals of 8 bits and stored for each address at intervals of 512 bits similar to the synchronous bits and when the serial data of 8 bits are written in the continuous addresses, the synchronous bits are discriminated for each address. <P>COPYRIGHT: (C)2004,JPO</p> |
